Tag: Invertor

Recent Articles- IJAERD

Low Power CMOS Inverter design at different Technologies

Author(s)– Vijay Kumar Sharma, Surender Soni

Abstract
The increasing prominence of portable systems and the need to limit power consumption and hence, power dissipation in very high density VLSI chips have led to rapid and innovative developments in low power design recently. Leakage control is becoming critically important for dep sub-100nm technologies due to the scaling down of threshold voltage and gate oxide thickness of transistors. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal.

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Recent Articles- IJAER

Comparison among different CMOS inverter for Low leakage at different Technologies
Author(s)– Vijay Kumar Sharma, Surender Soni

Abstract
In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. In the nanometer technology regime, power dissipation and Process parameter variations have emerged as major design considerations. These problems continue to grow with leakage power becoming a dominant form of power consumption. On the other hand, variations in the device parameters, both systematic and random, translate into variations in circuit parameters like delay and leakage. Leakage power dissipation is projected to grow exponentially in the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. Several techniques used that efficiently minimize this leakage power loss. Stacking is a leakage reduction technique.

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