Low Power CMOS Inverter design at different Technologies
Author(s)– Vijay Kumar Sharma, Surender Soni
Abstract
The increasing prominence of portable systems and the need to limit power consumption and hence, power dissipation in very high density VLSI chips have led to rapid and innovative developments in low power design recently. Leakage control is becoming critically important for dep sub-100nm technologies due to the scaling down of threshold voltage and gate oxide thickness of transistors. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal.
