Recent Articles- IJAER

Comparison among different CMOS inverter for Low leakage at different Technologies
Author(s)– Vijay Kumar Sharma, Surender Soni

Abstract
In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. In the nanometer technology regime, power dissipation and Process parameter variations have emerged as major design considerations. These problems continue to grow with leakage power becoming a dominant form of power consumption. On the other hand, variations in the device parameters, both systematic and random, translate into variations in circuit parameters like delay and leakage. Leakage power dissipation is projected to grow exponentially in the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. Several techniques used that efficiently minimize this leakage power loss. Stacking is a leakage reduction technique.

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